1. Field of the Invention
The present invention relates generally to capacitor structures formed within microelectronic fabrications. More particularly, the present invention relates to capacitor structures formed within semiconductor integrated circuit microelectronic fabrications.
2. Description of the Related Art
Microelectronic fabrications are formed from microelectronic substrates over which are formed patterned microelectronic conductor layers which are separated by microelectronic dielectric layers.
Common in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, is the use and the fabrication of memory cell structures, and in particular dynamic random access memory (DRAM) cell structures. Dynamic random access memory (DRAM) cell structures typically comprise a field effect transistor (FET) device formed within and upon a semiconductor substrate, where one of a pair of source/drain regions within the field effect transistor (FET) device has a storage capacitor formed thereover and electrically connected therewith. Within a dynamic random access memory (DRAM) cell structure, a gate electrode of the field effect transistor (FET) device serves as a wordline which provides a switching function for charge introduction into and retrieval from the storage capacitor, while the other of the pair of source/drain regions within the field effect transistor (FET) device serves as a contact for a bitline conductor layer which introduces or retrieves charge with respect to the storage capacitor.
While the dynamic random access memory (DRAM) cell structure has clearly become ubiquitous in the art of semiconductor integrated circuit microelectronic fabrication, and is thus essential in the art of semiconductor integrated circuit microelectronic fabrication, the dynamic random access memory (DRAM) cell structure is nonetheless not entirely without problems in the art of semiconductor integrated circuit microelectronic fabrication.
In that regard, as semiconductor integrated circuit microelectronic fabrication integration levels have increased and semiconductor device and patterned conductor layer dimensions have decreased, it has become increasingly difficult in the art of semiconductor integrated circuit microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to fabricate within dynamic random access memory (DRAM) cell structures of decreased dimension storage capacitors of increased capacitance.
It is thus desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, to provide methods and materials through which there may be fabricated within memory cell structures of decreased dimensions storage capacitor structures with increased capacitance.
It is towards the foregoing object that the present invention is directed.
Various memory cell structures having desirable properties, and methods for fabrication thereof, have been disclosed in the art of semiconductor integrated circuit microelectronic fabrication.
Included among the memory cell structures, but not limited among the memory cell structures, are memory cell structures disclosed within: (1) Morie et al., in U.S. Pat. No. 4,786,954 (a memory cell structure with enhanced integration density and enhanced electrical performance effected by fabricating within the memory cell structure a trench storage capacitor rather than a planar storage capacitor); (2) Hsia et al., in U.S. Pat. No. 6,008,515 (a memory cell structure having formed therein a storage capacitor with enhanced areal capacitance by forming a capacitor node dielectric layer into which is formed a capacitor node layer within the storage capacitor with a corrugated sidewall rather than a smooth sidewall); and (3) Cunningham, in U.S. Pat. No. 6,087,214 (a memory cell structure with enhanced integration density by fabricating within the memory cell structure a metal-insulator-semiconductor (MIS) capacitor upon a semiconductor substrate having formed therein a trench).
Desirable in the art of microelectronic fabrication, and in particular in the art of semiconductor integrated circuit microelectronic memory fabrication, are additional methods and materials through which there may be fabricated within memory cell structures of decreased dimensions storage capacitor with increased capacitance.
It is towards the foregoing object that the present invention is directed.
A first object of the invention is to provide a capacitor structure for use within a microelectronic fabrication.
A second object of the present invention is to provide a capacitor structure in accord with the first object of the present invention, wherein the capacitor structure may be fabricated with increased capacitance within a memory cell structure of decreased dimensions.
In accord with the objects of the present invention, there is provided by the present invention a method for fabricating a capacitor structure, and a capacitor structure fabricated in accord with the method.
To practice the method of the present invention, there is first provided a semiconductor substrate having formed therein an isolation region adjoining an active region of the semiconductor substrate. There is then etched the isolation region to form therein a laterally asymmetric trench bounded at one of its sides by a sidewall of the active region of the semiconductor substrate and at the remainder of its sides by a remaining portion of the isolation region. There is then formed into the laterally asymmetric trench a capacitor node layer which contacts the sidewall of the active region of the semiconductor substrate and rises above active region of the semiconductor substrate. There is then formed upon the capacitor node layer a capacitor dielectric layer. Finally, there is then formed upon the capacitor dielectric layer a capacitor plate layer.
The method of the present invention contemplates a capacitor structure fabricated in accord with the method of the present invention.
The present invention provides a capacitor structure for use within a microelectronic fabrication, wherein the capacitor structure may be fabricated with increased capacitance within a memory cell structure of decreased dimensions.
The present invention realizes the foregoing object by forming a capacitor structure in accord with the present invention within a laterally asymmetric trench within an isolation region which adjoins an active region of a semiconductor substrate such that a capacitor node layer when formed into the laterally asymmetric trench adjoins a sidewall of the active region of the semiconductor substrate and rises above a horizontal plane of the active region of the semiconductor substrate.